Input Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
data[] |
No |
Data input to the flipflops. |
Input port LPM_WIDTH wide. If the data[] input is not used, at least one of the aset, aclr, sset, sclr and/or the combination of shiftin and shiften ports must be used. |
clock |
Yes |
Positive-edge-triggered clock. |
|
enable |
No |
Clock enable input. |
If omitted, the default value is 1. |
shiftin |
No |
Serial shift data input. |
The shift options also use the enable input for the clock enable. For serial operation, the shiften and enable ports must be asserted high. |
shiften |
No |
Shift enable input. When asserted high (1), enables the shift operation. When asserted low (0), enables the register operation. |
If omitted, the default value is 0, register operation. |
sclr |
No |
Synchronous clear input. |
Clears the q[] outputs. If both the sset and sclr ports are used and asserted, the value of the sclr port is used. |
sset |
No |
Synchronous set input. |
Sets the q[] outputs to the value specified by the LPM_SVALUE parameter if that value is present, or sets the q outputs to all 1s. If both the sset and sclr ports are used and asserted, the value of the sclr port is used. |
aclr |
No |
Asynchronous clear input. |
Asynchronously clears the q[] outputs. If both the aset and aclr ports are used and asserted, the value of the aclr port is used. |
aset |
No |
Asynchronous set input. |
Sets q[] outputs to the value specified by the LPM_AVALUE parameter if that value is present, or sets the q[] outputs to all 1s. If both the aset and aclr ports are used and asserted, the value of the aclr port is used. |