Interconnect Parameters

The following parameters are available on the tab:
Table 1. Interconnect Parameters
Option Description
Limit interconnect pipeline stages to

Specifies the maximum number of pipeline stages that Platform Designer can insert in each command and response path to increase the fMAX at the expense of additional latency.

You can specify between 0 and 4 pipeline stages, where 0 means that the interconnect has a combinational datapath.

This setting is specific for each Platform Designer system or subsystem.
Clock crossing adapter type
Specifies the default implementation for automatically inserted clock crossing adapters:
Handshake This adapter uses a simple handshaking protocol to propagate transfer control signals and responses across the clock boundary. This methodology uses fewer hardware resources because each transfer is safely propagated to the target domain before the next transfer can begin. The Handshake adapter is appropriate for systems with low throughput requirements
FIFO This adapter uses dual-clock FIFOs for synchronization. The latency of the FIFO-based adapter is a couple of clock cycles more than the handshaking clock crossing component. However, the FIFO-based adapter can sustain higher throughput because it supports multiple transactions at any given time. FIFO-based clock crossing adapters require more resources. The FIFO adapter is appropriate for memory-mapped transfers requiring high throughput across clock domains.
Auto If you select Auto, Platform Designer specifies the FIFO adapter for bursting links, and the Handshake adapter for all other links.
Automate default slave insertion Directs Platform Designer to automatically insert a default slave for undefined memory region accesses during system generation.
Enable instrumentation When you set this option to TRUE, Platform Designer enables debug instrumentation in the Platform Designer interconnect, which then monitors interconnect performance in the system console.
Interconnect reset source Select Default or a specific reset signal in your design.
Burst adapter implementation
Allows you to choose the converter type that Platform Designer applies to each burst.
Generic converter (slower, lower area) Default. Controls all burst conversions with a single converter that is able to adapt incoming burst types. This results in an adapter that has lower fMAX, but smaller area.
Per-burst-type converter (faster, higher area) Controls incoming bursts with a particular converter, depending on the burst type. This results in an adapter that has higher fMAX, but higher area. This setting is useful when you have AXI masters or slaves and you want a higher fMAX.
Width adapter implementation
Generic converter (slower, lower area) Default. Controls all burst conversions with a single converter that is able to adapt incoming burst types. This results in an adapter that has lower fMAX, but smaller area.
Optimized converter (faster, higher area) Controls incoming bursts with a particular converter, depending on the burst type. This results in an adapter that has higher fMAX, but higher area. This setting is useful when you have AXI masters or slaves and you want a higher fMAX.
Enable ECC protection
Specifies the default implementation for ECC protection for memory elements.
FALSE Default. Disables ECC protection for memory elements in the Platform Designer interconnect.
TRUE Enables ECC protection for memory elements. Platform Designer interconnect sends uncorrectable errors arising from memory as DECODEERROR (DECERR) on the Avalon® response bus.
For more information about Error Correction Coding (ECC), refer to Error Correction Coding (ECC) in Platform Designer Interconnect.
Interconnect type
Allows you to select the implementation of Platform Designer interconnect. You can select one of the following options:
Standard Suitable for all devices
(Alpha release) Hyperflex-optimized Suitable for latency-tolerant Intel® Stratix® 10 applications. This option has higher potential fmax and bandwidth, at the expense of increased latency
Use synchronous reset When set to True, all registers in the interconnect use synchronous reset. Assert the reset for at least 16 cycles and start transactions 16 cycles after deassertion of the reset. This period allows all the IP components to reset and come out of the reset state. To avoid deadlocks in the interconnect, reset masters and slaves simultaneously. If masters and slaves have different resets, reset slaves only after responding to all necessary transactions. The Use synchronous reset option is enabled by default for Intel® Stratix® 10 devices, but is disabled by default for all other devices. Enabling synchronous reset for the interconnect does not enable synchronous reset for IP components in the system. You must separately enable the synchronous reset parameter for any component.