Set Clock Latency Dialog Box (set_clock_latency)

You access this dialog box by clicking Constraints > Set Clock Latency in the Timing Analyzer, or with the set_clock_latency Synopsys® Design Constraints (SDC) command.

Specifies additional delay (that is, latency) in a clock network. This delay value represents the external delay from a virtual (or ideal) clock through the longest (-late) or shortest (-early) path, with reference to the rising (-rise) or falling (-fall) clock transition. For setup analysis, the Timing Analyzer uses the late clock latency for the data arrival path and the early clock latency for the clock arrival path. For hold analysis, the Timing Analyzer uses the early clock latency for the data arrival time and the late clock latency for the clock arrival time.



The following sections provide more information about specifying options for this constraint:

Latency type (-late, -early, -rise, -fall):

Allows you to specify the type of latency in a clock network. The following options are available:

  • Late (-late)— Specifies an external delay value for the clock through the longest path with reference to the clock edge.
  • Early (-early)— Specifies an external delay value for the clock through the shortest path with reference to the clock edge.
  • Rise (-rise)— Specifies an external delay value for the clock with reference to the rising clock edge.
  • Fall (-fall)— Specifies an external delay value for the clock with reference to the falling clock edge.
  • Both— Directs the Timing Analyzer to use the same value for both options.

Delay value:

Specifies the clock latency value.

Targets:

Allows you to specify the targets to which the constraint applies. You can use the Name Finder (...) to build a collection Definition of targets.

SDC command:

Displays, and allows you to enter, SDC commands for the options you specify in this dialog box.