Enable Beneficial Skew Optimization logic option

A logic option that allows the Fitter to insert skew on globally routed clock signals to improve design performance.

This option is useful for optimizing timing results.

You can assign this option to any node that is a clock source or destination, including pins, PLL outputs, outputs of user-instantiated clock control blocks, combinational nodes made global automatically, and any register node. This option is available for supported device (Arria^® II, Cyclone^® IV, Stratix^® IV) families.