ID:13035 Inserted always-enabled tri-state buffer between "<name>" and its non-tri-state driver.
CAUSE: The Quartus Prime software expected the specified node to be driven by tri-state drivers, but the node is driven by non-tri-state logic. As a result, the Quartus Prime software inserted an always-enabled tri-state buffer between the node and the non-tri-state driver to make the netlist valid.
For example, the following Verilog design gives this warning:
module test1 (input in1, in2, in3, oe1, oe2, output out1, inout bi1, inout bi2); reg tri_wire; wire tmp_bidir; always @ (*) begin if (oe1) tri_wire <= in1; else if (oe2) tri_wire <= in2; else tri_wire <= 1'bZ; end assign out1 = tri_wire; assign bi1 = tri_wire; nand (tmp_bidir, bi1, in3); assign bi2 = tmp_bidir; endmoduleIn the design test1, the bidirectional pin bi2 is driven by non-tri-state logic. As a result, this warning will be given for that pin. The following design also gives this warning for the output pin out.
module test2 (input in1, in2, in3, oe1, oe2, output out); reg tri_wire; wire tmp_bidir; assign out = oe1 ? in1 : 1'bz; assign out = oe2 ? in2 : 1'bz; assign out = in3; endmodule
ACTION: Remove the non-tri-state logic feeding the node.