ID:276027 Inferred dual-clock RAM node "<name>" from synchronous design logic. The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
module dual_clock_ram ( input rclk, wclk, we, input [7:0] data, input [5:0] raddr, waddr, output [7:0] q ); reg [5:0] raddr_reg; reg [7:0] ram[0:63]; always@(posedge wclk) begin if(we) ram[waddr] <= data; end always@(posedge rclk) begin raddr_reg <= raddr; end assign q = ram[raddr_reg]; endmoduleIn this example, a read-during-write or a read that closely follows a write should return the newly written data. When implemented in a memory block in the target device, the write cycle is not complete before the read begins. Consequently, the dual-clock inferred by Analysis & Synthesis requires two read cycles to access the correct data at the memory location. A mismatch may also occur if the read and write clocks derive from the same clock source. For example, you connected the pins that feed the read and write clocks to the same clock source on your board, or you created a design partition that make the clocks appear distinct to Analysis & Synthesis. That is, they are ports on the design partition boundary but they are fed by the same source in the parent partition. In simulation, the RAM has a specific read-during-write behavior that will not be matched by the implementation in the memory blocks of the target device.
ACTION: If your design does not depend on the RAM's read-during-write behavior, no action is required. To avoid receiving this message, apply the ramstyle synthesis attribute with the value "no_rw_check" to the RAM in your design file. You can also replace the registers and address logic with an explicit instantiation of the altsyncram megafunction. If you are concerned about a potential mismatch, you can prevent Analysis & Synthesis from converting the registers into an altsyncram megafunction by turning off the Auto RAM Replacement logic option for the entity or instance that contains the dual-clock RAM. Intel advises against turning off the option globally as it prevents the software from inferring all RAMs, which may negatively impact the area and performance of your design.