ID:18708 ATX/FPLL < <name> > is not placed in the same bank as the reference clock.
CAUSE: For the best jitter performance, Intel recommends using a reference clock within the same bank as the transceiver PLL (ATX PLL, fPLL) that the reference clock is driving.
ACTION: If possible, put the ATX PLL or fPLL in the same bank as reference clock in Assignment Editor.