ID:10629 VHDL error at <location>: can't synthesize logic for statement with conditions that test for the edges of multiple clocks
CAUSE: In a VHDL Design File (.vhd) at the specified location, you referred to more than one distinct clock edge in the conditions of an If Statement or a Conditional Signal Assignment. As a result, the statement tests for the edges of more than one clock. For example, in the following code, the If Statement contains a condition that tests for the rising edge of clk1, and contains another condition that tests for the rising edge of clk2:
PROCESS (clk1, clk2, reset) BEGIN IF (reset = '0') THEN Q1 <= '0'; Q2 <= '0'; ELSE IF (rising_edge(clk1)) THEN Q1 <= data1; ELSE IF (rising_edge(clk2)) THEN Q2 <= data2; END IF; END PROCESS;Because the statement tests for the clock edges of multiple clocks, the Quartus Prime software cannot synthesize logic for the statement.
ACTION: Factor the statement into multiple statements that each test for the edges of a single clock. For the previous example, you can use the following code:
PROCESS (clk1, clk2, reset) BEGIN IF (reset = '0') THEN q1 <= '0'; ELSE IF (rising_edge(clk1)) THEN q1 <= data1; END IF; IF (reset = '0') THEN q2 <= '0'; ELSE IF (rising_edge(clk2)) THEN q2 <= data2; END IF; END PROCESS;