ID:10258 Verilog HDL error at <location>: unsupported type for Verilog parameter <param_name>
CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), a Verilog parameter received a value of a type not supported by Verilog. For example if we pass an enumeration from VHDL, this error message will be given.
Example of mixed language parameter passing with incompatible types:
LIBRARY ieee; USE ieee.std_logic_1164.all; entity convert4 is Port ( o : OUT STD_LOGIC ); END convert4; ARCHITECTURE rtl OF convert4 IS component vlg_param Generic ( p1 : boolean := false ); Port ( o : OUT STD_LOGIC ); end component; begin inst1 : vlg_param; end rtl;And the Verilog module that receives the Boolean parameter:
module vlg_param(output o); parameter p1 = 1; endmodule
ACTION: Do not pass unsupported value types to Verilog.