ID:13317 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: rising or falling edge is not allowed in combinational UDP "<name>"
CAUSE: In the specified User-Defined Primitive (UDP) Declaration at the specified location in a Verilog Design File (.v), you used a rising or falling edge; however, rising or falling edges are not allowed in combinational UDPs.
ACTION: Edit the design to remove the rising or falling edge from the specified UDP.