Fitter Resource Utilization by Entity Report

All Device Families ExceptArria® V , Cyclone® V , and Stratix® V

Reports the utilization of resources for each entity in the compilation hierarchy. The Compilation Hierarchy Node lists the names of the nodes in the design. For table entries with two numbers listed, the numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. The numbers in parentheses indicate the number of resources of the given type used by the node in that row.

Types of resources include Combinational Adaptive Look-Up Table (ALUT) Definition, Memory ALUTs, LUT_REGs,logic utilization of Adaptive Logic Module (ALM) Definition, dedicated logic registers, I/O registers, logic cell Definition, register Definition, block memory bits, memory bit DefinitionM512 memory blocks, M144K memory block Definition, M20k memory blocks, M4K memory blocks, M-RAM Definition,macrocell Definition,DSP block Definition, DSP block 9x9, 12x12 18x18, and 36x36 multipliers, virtual pins Definition, pins, carry chain logic cells, logic cells that only utilize the LUT in the logic cell, logic cells that only use the register, and logic cells that use both register and LUT, combinational with no register ALUT/register pair, register-only ALUT/register pair, combinational with a register ALUT/register pair, and the full hierarchy name. The specific resources listed in the report may vary depending on the device selected.

The Compilation Report list can contain multiple Resource Utilization by Entity reports, one generated during Synthesis, partition based reports, and one generated during fitting. The Synthesis Resources Reports show the resource usage of entities in the compilation hierarchy as calculated after logic synthesis, but before fitting. Because the Fitter's register packing Definition operation may reduce the number of logic cells in the design, the total usage reported in the Synthesis Resource Utilization by Entity report might be greater than the total usage reported in the Fitter Resource Utilization by Entity report or the Fitter Resource Usage Reports.

Note: The Logic Cells, LUT-Only LCs, Register-Only LCs, LUT/Register LCs and Carry Chain LCs columns list the logic cells used all entities (including the top level design entity) and the number of logic cells (in parentheses) used by the design entity at that level in the hierarchy.

The logic cell combinational count may be inaccurate if the inputs or outputs of an entity are not registered. Having unregistered inputs and outputs can cause logic to be optimized across entity boundaries, which means that logic that was originally in one entity may be named after logic in an adjacent entity and may thus be accounted towards the wrong entity.

Arria® V, Cyclone® V , and Stratix® V Device Families

The Fitter Resource Utilization by Entity report forArria® V , Cyclone® V , and Stratix® V device families describes logic utilization in terms of ALMs needed.

Important: The computation of ALMs needed results per hierarchy node displays as a fractional number because the ALM may contain logic belonging to more than one hierarchy. For example, if a particular ALM implements four elements from one hierarchy node and one element from a second node, .80 of an ALM is attributed to the first hierarchy node and the remaining .20 of the ALM is attributed to the second hierarchy node..

ALMs needed—calculated from the result of:

ALMs used in final placement – Estimate of ALMs recoverable by dense packing + Estimate of ALMs unavailable

  • ALMs used in final placement—Calculated as the sum of ALM usage as LUT logic and registers, logic only, registers only, and memory.
  • Estimate of ALMs recoverable by dense packing—An estimate of the number ALMs which can be recovered as the design grows. This metric estimates the amount of recoverable logic in units of ALMs. During Place and Route optimization, the Intel® Quartus® Prime software permits logic to use more area than is required, improving optimization metrics such as Fmax. However, as the design grows and more logic is added, you may need to know what amount of that space can be recovered.
  • Estimate of ALMs unavailable—An estimate of ALMs that are not used by a specified entity, but are likely not available for usage due to various design and device constraints. The Estimate of ALMs unavailable metric is based on the following factors; ALMs may be unavailable due to location constrained logic, LAB-wide signal conflicts, LAB input limits, or due to virtual I/Os.
    Note: Estimate of ALMs unavailable for a given entity, depends on how the design as a whole is implemented. For example, if the entity is compiled by itself, all of the estimated unavailable logic is attributed to it. If that same entity is compiled with other entities, the estimated unavailable logic will be distributed among all the entities. You should expect to see different estimates of unavailable resources for a given entity depending on how the design is physically implemented.

ALMs used for memory—Lists the number of ALMs used to implement memory bits in core logic.

For more information on how the Intel® Quartus® Primesoftware calculates logic utilization see the Fitter Resource Usage Summary report in this topic.