Insert Template Dialog Box

You open this dialog box by clicking Insert Template on the Edit menu with a file open in the Intel® Quartus® Prime Text Editor.

Allows you to insert a Verilog HDL, SystemVerilog, VHDL, AHDL, Intel® Quartus® Prime Tcl, Tcl, Timing Analyzer design constraints, or Intel® FPGA IP template in a text file at the current insertion point or in place of selected text. Additionally, to ease the specification of timing constraints in the Timing Analyzer, the Intel® Quartus® Prime Text Editor supports Synopsys® Design Constraints (SDC) templates.

In the Language templates pane, the Intel® Quartus® Prime software organizes templates according to their language and purpose. You can make changes to a template in the Preview pane before you insert it into your code; however, you cannot save changes to an Intel-provided template. If you want to save changes, you can save the template as a user template below any language entity. You can specify the directory where you want to save user templates in the Text Editor page in the Options dialog box.