Generate Example Design (Generate Menu) (Platform Designer)

You can generate a Platform Designer example design by clicking Generate > Generate Example Design.

The example design provides the top-level HDL definition of your Platform Designer system in either Verilog HDL or VHDL. This tab also displays VHDL component declarations. You can copy this HDL example and paste it into a top-level HDL file that instantiates the Platform Designer system, if the system is not the top-level module in your Intel^® Quartus^® Prime project.