EDA Netlist Writer Simulation Reports:

Simulation Settings Report

Reports the simulation settings you specified in theSettingsdialog box (Assignments menu).

• Tool Name shows the name of the Third Party EDA tool and HDL design file type you specified.
• Time scale shows the time scale you specified for this compilation.
• Truncate long hierarchy paths shows the setting you specified for the Truncate long hierarchy paths option.
• Map illegal HDL characters shows the setting you specified for the Map illegal HDL characters option.
• Flatten buses into individual nodes, shows the setting you specified for the Flatten buses into individual nodes option.
• Maintain hierarchy, shows the setting you specified for the Maintain hierarchy option.
• Bring out device-wide set/reset signals as ports, shows the setting you specified for the Bring out device-wide set/reset signals as ports option.
• Enable glitch filtering shows the setting you specified for the Enable glitch filtering option.
• Generate Power Estimate Scripts shows the option you specified in the Generate Value Change Dump file scriptoption.
• Test Bench design instance nameshows the test bench design instance name you specified when you created anew test benchfile.
• Do not write top level VHDL entity shows the setting you specified for the Do not write top level VHDL entity option.
• Disable setup and hold time violations detection in input registers of bidirectional pins shows the setting you specified for the Disable setup and hold time violations detection in input registers of bidirectional pins option.
• Architecture name in VHDL output netlist shows the name you specified in the Architecture name in VHDL output netlist option.

Generated Files Report

Lists files generated by the EDA Netlist Writer for use with Simulation tools.