Synthesis logic options Related concepts Add Pass-Through Logic to Inferred RAMs logic option Allow Any RAM Size For Recognition logic option Allow Any ROM Size For Recognition logic option Allow Any Shift Register Size For Recognition logic option Allow Synchronous Control Signals logic option Shift Register Replacement - Allow Asynchronous Clear Signal logic option Auto Carry Chains logic option Auto Clock Enable Replacement logic option Auto DSP Block Replacement logic option Auto Open-Drain Pins logic option Auto Packed Registers logic option Auto RAM Block Balancing logic option Auto RAM Replacement logic option Auto Shift Register Replacement logic option Block Design Naming logic option Carry Chain Length logic option Clock MUX Protection logic option Disable Register Merging logic option Extract Verilog State Machines logic option Extract VHDL State Machines logic option Force Use of Synchronous Clear Signals logic option HDL Initial Fan-out Limit logic option HDL Message Level logic option Ignore CARRY Buffers logic option Ignore CASCADE Buffers logic option Ignore LCELL Buffers logic option Ignore Maximum Fan-Out Assignments logic option Ignore SOFT Buffers logic option Ignore translate_off and synthesis_off Directives logic option Ignore Verilog Initial Constructs logic option Implement as Clock Enable logic option Implement as Output of Logic Cell logic option Iteration limit for constant Verilog loops logic option Logic Cell Insertion logic option Maximum Fan-Out logic option Maximum Number of M4K/M9K/M20K/M10K Memory Blocks logic option NOT Gate Push-Back logic option Number of Removed Registers Reported in Synthesis Report logic option