Plan Stage Reports

The Plan stage reports describe the I/O, interface, and control signals discovered during the periphery planning stage of the Fitter.
Figure 1. Plan Stage Reports (Intel® Arria® 10 and Intel® Cyclone® 10 GX Designs)

For Intel® Arria® 10 and Intel® Cyclone® 10 designs, the Plan stage includes the Global & Other Fast Signals Summary report that allows you to verify which clocks the Compiler promotes to global clocks. Clock planning occurs after the Early Place stage for Intel® Stratix® 10 designs.