Synopsys Design Constraints File (.sdc) Definition

An ASCII text file (with the extension .sdc) that contains design constraints and timing assignments in the industry-standard Synopsys^® Design Constraints format. The constraints in a Synopsys^® Design Constraints File are described using the Tcl tool command language and follow Tcl syntax rules.

You must create an SDC File to specify timing constraints when running the Timing Analyzer. You can create an SDC File by either entering Tcl commands in the Console or with the commands and dialog boxes in the Timing Analyzer's graphical user interface. The SDC File should only contain SDC commands. You can use Tcl statements, but only those from the ::quartus::sdc 1.5 package.

You can create an SDC File to specify timing constraints when running the Synopsys^® PrimeTime software from within the Intel^® Quartus^® Prime software on Linux workstations. You can specify the name of the SDC File in the More Timing Analysis Settings dialog box, which is available from the Timing Analysis page under EDA Tool Settings in the Settings dialog box. You can also use SDC Files with the Mentor Graphics^® Precision RTL Synthesis software to specify design constraints.

The SDC File that is defined in the Synopsys^® Design Constraints format is different from the Synplify Design Constraints File (even though both files share the same file extension).

For a sample SDC File, refer to The Intel^® Quartus^® Prime TImeQuest Timing Analyzer chapter of the Intel^® Quartus^® Prime handbook.