M20K memory block Definition
A synchronous, true dual-port memory block, with registered inputs and optionally registered outputs, available in Stratix® V family devices. You can use the M20K block for storing processor code, implementing lookup schemes, and implementing large memory applications. Each block is a 512 × 40 RAM block and contains 20,480 programmable bits, including parity bits. You can configure the M20K block as true dual-port, simple dual-port, and single-port RAM, and ROM. You can use a Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) to preload the memory contents when the M20K memory block is configured as a RAM or ROM. All RAM instances are kept in the form of RAM slices until after analysis and synthesis, when the Fitter assigns RAM slices to M20K RAM blocks or MLABs to balance out the resource usage, or if the design specifies MLAB.
Each M20K memory block supports three clock-enable controls, which allows each input register and core memory cell to use either clock-enable controls or no gating clock control. The output register supports one clock-enable control or no gating clock control. Clock muxing is balanced, which prevents skew between clock paths.
The Write Enable (WE) and Read Enable (RE) controls are independent in M20K memory blocks. Independent WE and RE controls allow you to reduce power consumption when data output during a write operation is not critical. Byte Enable (BE) signals allow for more fine-grained write control.
The following table lists the configurable sizes for the M20K memory block
|
Operation Mode |
M20K Memory Block Size |
|---|---|
|
Single port or ROM |
16K × 1 8K × 2 4k × 4 4K × 5 2K × 8 2K ×10 1K x 16 1K x 20 512 x 32* 512 x 40* |
|
Dual-port |
Write × M / Read × N Write × Y / Read × Z M, N= 1, 2, 4, 8, 16, or 32 Y, Z= 5, 10, 20, 40 |
|
True dual-port |
port A × M / port B × N A × Y / B × Z M, N = 1, 2, 4, 8, or 16 Y, Z = 5, 10, or 20 |
* The widest single-port mode is supported by emulation through true dual-port mode. The Intel® Quartus® Prime software packs two atoms (each with half data width) in true dual-port mode to support the widest mode.
The widest ROM mode is implemented through simple dual-port mode, instead of packed-mode implementation for single-port mode. This implementation is used mainly to save power, because ROM requires only one port (read-port) and power is saved by disabling the activities in other port (write-port).