Active Parallel configuration scheme (AP) Definition
A configuration scheme in which the active parallel memory configuration interface block loads design data into one or more Cyclone® III devices. In this scheme, the active parallel memory configuration interface block in the Cyclone® III device controls the configuration process, and configures all of the devices in the chain using the configuration data stored in a parallel flash device.
The Intel® Quartus® Prime Compiler automatically generates SRAM Object Files (.sof) that contain the data for configuring Intel devices in an active parallel configuration scheme.