Shapes tab

Assignments Logic Lock Region Shapes

• Placement Shape—Shows the dimensions and origin of the placement region, as described in the Intel^® Quartus^® Prime Settings File (.qsf). The Fitter uses these constraints the next time you compile.
• Routing Shape—Appears when the Routing Region os not Unconstrained. Shows the dimensions and origin of the placement region, as described in the Intel^® Quartus^® Prime Settings File (.qsf). The Fitter uses these constraints the next time you compile.
• Routing type—Allows you to select the routing type for the routing region. Logic Lock regions support the following routing types:

  Table 1. Routing Region Options

  Option	Description
  Unconstrained (default)	Allows the fitter to use any available routes on the device.
  Whole Chip	Same as Unconstrained, but writes the constraint in the Intel® Quartus® Prime settings file (.qsf).
  Fixed with Expansion	Follows the outline of the placement region. The routing region scales by a number of rows/cols larger than the placement region.
  Custom	Allows you to make a custom shape routing region around the Logic Lock region. When you select the Custom option, the placement and routing regions move independently in the Chip Planner. In this case, move the placement and routing regions by selecting both using the Shift key.

Show Compilation Logic Lock Region Shapes

If you enable the option, the Shapes tab displays Placement Shape and Routing Shape defined in the last compilation.

The assignments and compilation settings differ when you refine your floorplan by adjusting the Logic Lock regions and assignments.