Verilog HDL Example Instantiation

module test_inbuf_diff (in, in_n, out);
input in,in_n;
output out;
alt_inbuf_diff inst1(.i(in), .ibar(in_n), .o(out));
defparam inst1.io_standard = "LVDS";
defparam inst1.location = "IOBANK_1";
defparam inst1.weak_pull_up_resistor = "off";
defparam inst1.enable_bus_hold = "off";
endmodule