Allow Synchronous Control Signals logic option

Allows the Compiler to use synchronous clear and/or synchronous load signals in normal mode logic cells. Turning on this option helps to reduce the total number of logic cells used in the design, but might negatively impact fitting since synchronous control signals are shared by all logic cells in a LAB.

This option is useful for finding areas of the design that can be implemented more efficiently with synchronous clear and/or synchronous load signals in normal mode logic cells, and as a result, minimize the number of logic cells used in the design.

This option must be assigned to either a design entity or a register or it is ignored. This option is available for all Intel devices supported by the Intel^® Quartus^® Prime software.