Generate HDL (Generate Menu) (Qsys Pro)
You open this dialog box in Qsys Pro by clicking .
The Quartus® Prime software uses Qsys Pro-generated synthesis HDL files during compilation. You can generate simulation HDL files, which can include simulation-only features targeted towards your simulator. You can generate simulation files as Verilog or VHDL, for use in your simulation environment. The Generation dialog box allows you to choose options to generate Qsys Pro design files for synthesis and simulation.
Note: For more information about
simulating a Qsys Pro system, refer to "Simulating a
Qsys Pro System" in the Creating a System in Qsys Pro chapter in volume 1 of the
Quartus® Prime Handbook, and the Simulating Intel Designs chapter in volume 3 of the
Quartus® Prime Handbook.