Verilog HDL Definition

The Verilog Hardware Description Language (Verilog HDL) is a language that describes the behavior of electronic circuits, most commonly digital circuits. Verilog HDL is defined by IEEE standards. There are three common variants: Verilog 1995, Verilog 2001, and the recent SystemVerilog 2005. You can use Verilog HDL for designing hardware and for creating test entities to verify the behavior of a piece of hardware. Verilog HDL is used as an entry format by a variety of EDA tools, including synthesis tools such as Quartus^® Prime Integrated Synthesis, simulation tools, and formal verification tools.