MAX^® V Definition

An Intel device family designed as a cost-effective solution for control path applications. The MAX^® V device architecture provides an instant-on, non-volatile architecture and includes a User Flash memory (UFM) block of 8,192 bits for non-volatile storage. MAX^® V devices feature low standby and dynamic power, MultiVolt I/O interface, hot socketing, internal oscillator, and memory functionality.

Each MAX^® V device contains a single UFM block, which is an 8192-bit version. MAX^® V devices also offer an optional digital PLL, which is optional intellectual property (IP) that can be instantiated and optional RAM implementation using available LEs.

The MAX^® V routing structure provides fast propagation delay and clock-to-output times. I/O standard support includes the 3.3-V PCI I/O standard, and LVCMOS and LVTTL I/O standards at 3.3 V, 2.5 V, 1.8 V, 1.5 V, and 1.3 logic levels. The input buffer for each MAX^® V device I/O pin has an optional Schmitt Trigger Input I/O standard settings at 2.5-V and 3.3-V LVTTL. The Schmitt trigger allows input buffers to respond to slow input edge rates with a fast output edge rate.

MAX^® V devices have an internal linear voltage regulator, which supports an external supply voltages of 1.8V.