macrocell Definition

A basic building block in supported device(MAX3000 and MAX7000) family devices. A macrocell is also generally known as a logic cell.

In MAX3000 and MAX7000 devices, a macrocell is a basic building block that consists of five product terms and a configurable register, and can be configured individually for either sequential or combinational logic operation. A macrocell consists of three functional blocks: the logic array, the product-term select matrix, and the programmable register.

The product"“term select matrix of a MAX3000 or MAX7000 macrocell allocates product terms for use as either primary logic inputs (to the OR and XOR gates) to implement combinational functions, or as secondary inputs to the macrocell"™s register preset, clock, and clock enable control functions.

Each programmable register of a MAX3000 or MAX7000 macrocell can be programmed individually to implement D, T, JK, or SR operation with programmable clock control; or bypassed entirely for combinational operation. During design entry, you specify the desired register type; the Quartus^® Prime software then selects the most efficient register operation for each registered function to optimize resource utilization. The Quartus^® Prime software or other synthesis tools can also select the most efficient register operation automatically when synthesizing HDL designs.

The programmable register can be clocked by one of the following clocks:

• A global clock.
• A global clock enabled by an active-high clock enable that is generated by a product term.
• An array clock that is implemented with a product term.

MAX3000 and MAX7000 devices contain two global clocks, each of which can be the true or the complement of one of the two global clock pins, GCLK1 or GCLK2.

The programmable register also supports asynchronous preset and clear functions. The product"“term select matrix allocates product terms to control these operations. Although the preset and clear from the register are active-high, you can use the signals as active"“low by inverting the signal within the logic array. In addition, each register clear function can be individually driven by the active"“low dedicated global clear (GCLRn).

Macrocells have "numbers" of the following format: