M144K memory block Definition

A synchronous, true dual-port memory block, with registered inputs and optionally registered outputs, available in supported device ( Arria^® II and Stratix^® IV) family devices. The M144K block is useful for storing processor code, implementing lookup schemes, and implementing large memory applications. Each block is a 2000 × 72 RAM block and contains 147,456 programmable bits, including parity bits. You can configure the M144K block as true dual-port, dual-port, and single-port RAM, and ROM. You can use a Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) to preload the memory contents when the M144K memory block is configured as a RAM, ROM, or MLAB. All RAM instances are kept in the form of block RAM until after analysis and synthesis, when the Fitter converts block RAM to M-LABs to balance out the resource usage, or if the design specifies MLAB.

The M144K memory block supports the Error Correction Code (ECC) feature in dual-port mode with 64-bit data. The feature performs single and double error detection, and performs single-bit error correction.

Each M144K memory block supports two clock-enable controls, which allows each input register and core memory cell to use either clock-enable controls or no gating clock control. The output register supports one clock-enable control or no gating clock control.

The Write Enable (WE) and Read Enable (RE) controls are independent in M144K memory blocks. Independent WE and RE controls allow you to reduce power consumption under circumstances when data output during a write operation is not critical.

The following table lists the configurable sizes for the M144K memory block: