Late Clock Latency timing assignment Definition

Specifies additional delay (latency) in a clock network. This delay represents the external delay from a virtual (or ideal) clock through the longest path. The Timing Analyzer uses the more conservative latency value. For setup analysis, the Timing Analyzer uses the late clock latency value for each source register. For hold analysis, the Timing Analyzer uses the late clock latency value for each destination register. You can assign the Late Clock Latency timing assignment to a clock signal in the design. To direct the Timing Analyzer to report the results of clock latency, you must turn on the Enable Clock Latency option in the More Timing Settings dialog box. When this option is turned on, the Timing Analyzer reports clock latency as clock skew in the reports listed in the Timing Analyzer folder of the Compilation Report. The Timing Analyzer ignores early and late clock latency on a clock when analyzing paths between registers within the same clock domain.

The affect of assigning a Late Clock Latency of 2ns to the clk1 clock pin is shown below: