hierarchical node name Definition

The unique name for a node or symbol that is based on the node or symbol's corresponding top-level design entity and the instance name or the AHDL, VHDL, or Verilog HDL instance name of the logic function to which the node or symbol is connected. The hierarchical node name has the following format:

<top-level design entity name>:<instance name>

Hierarchical node names can contain an unlimited amount of characters, including vertical bar (|), colon (:), and period (.). Case is not significant, except in Verilog HDL.

Every node and symbol in a project has a hierarchical name. You can also assign a node name to a node.