gated clock signal Definition
A clock configuration in which the output of an AND
or OR
gate drives a clock. The
Quartus® Prime
software also recognizes undefined ripple clocks (that is, clocks
driven by the output of a register for which no clock setting is
assigned) as gated clocks. Intel recommends that you use clock
enables rather than gated clocks in a design to prevent clock skew
and internal hold violations.