Cyclone 10 LP Device Definition

An Intel device family that is a cost-effective solution for data path applications. The Cyclone^® 10 LP device architecture supports M9K memory blocks to implement single-port, dual-port, and true dual-port memory. Cyclone^® 10 LP devices also contain embedded multiplier blocks that enable efficient implementation of high-performance filters and multipliers.

The memory blocks of a Cyclone^® 10 LP device can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port RAM, and single-port RAM, ROM, and shift registers.

Cyclone^® 10 LP devices are available with core voltages of 1.0 V and 1.2 V.

Cyclone^® 10 LP devices provide up to eight PLLs per device, which provide advanced multiplication, programmable duty cycle, phase shifting, programmable bandwidth, manual clock switchover, clock outputs driving all networks, and normal and zero delay buffer modes. Cyclone^® 10 LP devices also provide up to 20 global clock lines that drive the global clock network throughout the entire device.

Cyclone^® 10 LP devices support numerous single-ended and differential I/O standards.