Clock Control Block Definition
The Clock Control Block controls each global and regional clock in supported device
(
Arria®
series,
Cyclone® IV,
Stratix® IV, and
Stratix® V ) families, allowing you to select between
clocks on every clock network and dynamically power down the clock network. Although
the
Fitter automatically implements Clock Control Blocks during placement of the design,
if you
want to control the clocks in a design or power down a clock network, you must instantiate
a Clock Control Block using the altclkctrl
megafunction.
When selecting the clock source, you can select between two
different PLLs clock outputs, two clock outputs of the same PLL,
two clock pins, or a combination of clock pins and PLL clock
outputs. The inclk[0]
and inclk[1]
ports
of the Clock Control Block need to be driven by clock pins and the
inclk[2]
and inclk[3]
ports need to be
driven by a PLL clock output.