Arria^® V Device Family Definition

An Intel device family based on a scalable architecture. Arria^® V devices have dedicated gigabit transceiver block (GXB) circuitry that includes up to 36 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded serializer/deserializer (SERDES) capability at data rates up to 10 Gbps. Arria^® V devices also provide dedicated circuitry that support differential I/O standards at up to 1.25 Gbps when using dynamic phase alignment (DPA). Arria^® V devices also provide fractional PLLs and regional, global, and periphery clock networks to increase performance, and provide advanced clock interfacing and clock-frequency synthesis.

Arria^® V GX devices offer up to 36 6-Gbps transceivers, LVDS at 1.25 Gbps, and support for 1.333 Gbps memory interfaces with low latency, and support for all mainstream single-ended and differential I/O standards, including 3.3 V. Arria^® V GT devices offer eight 10-Gbps transceivers, LVDS at 1.25 Gbps, and support for 1.333 Gbps memory interfaces with low latency, and support for all mainstream single-ended and differential I/O standards, including 3.3 V.

The Arria^® V family device architecture supports two RAM block sizes, which are the M10K memory blocks and the MLAB. M10K memory blocks implement single-port, dual-port, and true dual-port memory. MLABs implement single-port and dual-port memory. Arria^® V family devices offer support for remote configuration updates. Arria^® V family devices also contain embedded DSP blocks that enable efficient implementation of high-performance filters and multipliers. The Adaptive Logic Module (ALM) of the Arria^®Vdevice family architecture provides advanced features with efficient logic utilization.

Arria^® V family devices support multiple I/O transfer protocols, XSBI, serial peripheral interface (SPI), Serial RapidIO, and Gigabit Ethernet (GbE). These protocols provide high-speed communication with application-specific standard products (ASSPs), application-specific integrated circuits (ASICs), and other programmable logic devices (PLDs). You can use both PCI Express hard IP and PCI Express soft IP to implement the physical layer, data link layer, and transaction layer of the PCI Express protocol stack. The PCI Express hard IP uses embedded dedicated logic to implement the PCI Express protocol stack.

Arria^® V family devices provide up to 16 fractional PLLs for each device. Arria^® V family fractional PLLs are capable of implementing real-time reconfiguration,clock switchover,advanced clock multiplication parameters,and fine-grain phase shifting.

Arria^® V family devices support numerous single-ended and differential I/O standards.

The memory blocks of Arria^® V family devices can implement shift registers and various types of memory with or without parity bits, including dual-port, true dual-port, and single-port RAM; ROM; FIFO buffers; and shift registers. In addition, Arria^® V family device I/Os have dedicated circuitry to assist with the implementation of high-speed interfaces to external memory devices such as double data rate (DDR) synchronous dynamic RAM (SDRAM), DDR 2 SDRAM, DDR 3 SDRAM, DDR 3L SDRAM, DDR 3U SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, DDRII SRAM, DDR II+ SRAM, QDR II+ SRAM, and RLDRAM II.