Arria 10 Device Family Definition

The Arria 10 device family consists of high-performance and power-efficient 20-nm mid-range FPGAs and SoCs.

Arria 10 device family contains a combination of 20-nm process technology and architectural advances provide the following benefits:

  • Performance improvement of 60% over previous generations of mid-range FPGAs and 15% higher performance than the fastest FPGA in the prior generation.
  • Power efficiency attained through a comprehensive set of power-saving technologies.
  • Significant reduction in die area and power consumption.
  • Increase of up to two times in transceiver I/O density compared to previous generation devices while maintaining optimal signal integrity.
  • You can configure up to 6 transceiver channels to run as fast as 25.8 Gbps on GT devices.
  • All channels feature continuous data rate support up to the maximum rated speed.
The Arria 10 devices are ideal for high performance, power-sensitive, midrange applications in diverse markets such as:
  • Wireless
  • Wireline
  • Broadcast
  • Computing and Storage
  • Medical
  • Military

The Arria 10 device family is available in three variants:

  • Arria 10 GX—an FPGA featuring 17.4 Gbps transceivers for short reach applications with 12.5 Gbps backplane driving capability.
  • Arria 10 GT—this variant features:
    • 17.4 Gbps transceivers for short reach applications with 12.5 Gbps backplane driving capability.
    • 25.8 Gbps transceivers for supporting CAUI-4 and CEI-25G applications with CFP2 and CFP4 modules.
  • Arria 10 SX—an SoC device integrating ARM-based HPS and FPGA featuring 17.4 Gbps transceivers for short reach applications with 16.0 Gbps backplane driving capability.

The Arria 10 family device architecture supports

  • Two RAM block types:
    • M20K memory blocks feature hard error correction code (ECC).
    • MLABs implement single-port and dual-port memory.
  • Support for remote configuration updates.
  • Embedded variable-precision DSP blocks that enable precision signal processing from 18x9 to 54x54, as well as floating point arithmetic with a wide variety of modes.
  • Adaptive Logic Modules (ALMs) provides enhanced 8-input ALM with four registers and hierarchical core clocking architecture.
  • Device I/Os have dedicated circuitry to assist with the implementation of high-speed interfaces to external memory devices such as DDR4, DDR3, and DDR3L.
  • A soft-memory controller with configurable support for RLDRAM 3, QDR IV, and QDR II+.

Arria 10 devices can be designed with high bandwidth, throughput, and low latency transcievers:

  • Up to 96 transciever channels for GX devices.
  • Up to 72 transciever channels for GT devices.
Arria 10 devices deliver the industry's lowest power consumption per transceiver channel:
  • 12.5 Gbps transceivers at as low as 242 mW
  • 10 Gbps transceivers at as low as 168 mW
  • 6 Gbps transceivers at as low as 117 mW

Arria 10 transceivers support various data rates according to application:

  • Chip-to-chip and chip-to-module applications—from 125 Mbps up to 25.8 Gbps
  • Long reach and backplane applications—from 125 Mbps up to 12.5 Gbps with advanced adaptive equalization
  • Critical power sensitive applications—from 125 Mbps up to 11.3 Gbps using lower power modes
Arria 10 support the following PCI Express®( PCIe®) hard IP with complete protocol stack, endpoint, and root port:
  • PCI Express® Gen3 (x1, x2, x4, or x8)
  • PCI Express® Gen2 (x1, x2, x4, or x8)
  • PCI Express® Gen1 (x1, x2, x4, or x8)

The Arria 10 system-on-a-chip (SOC) contains a second generation hard processor system (HPS) with an integrated ARM® Cortex™ A9 MPCore processor. This design provides tight integration of a dual-core processor, hard IP, and an FPGA. All members of the device family can operate at a peak bandwidth of 128 Gbps with integrated data coherency between the processor and the FPGA fabric.