Logic Options Definition
The following logic options are available in the Quartus® Prime software.
Advanced logic options:
Global Signals logic options:
I/O Features logic options:
- Auto Open-Drain Pins
- CKn/CK Pair
- Current Strength
- DQ Group
- DQS Frequency
- DQSn/DQS Pair
- Dynamic Termination Control Group
- Electromigration Current
- Enable Bus-Hold Circuitry
- Force PLL Output Counter
- I/O Placement Optimizations
- I/O Standard
- In-System Programming Clamp State
- Input Reference
- Input Termination
- Memory Interface Data Pin Group
- Output Enable Group
- Output Pin Load
- Output Termination
- PLL Compensation
- PLL Ignore Migration Devices
- Preserve PLL Counter Order
- Programmable Differential Output Voltage (VOD)
- Programmable Pre-emphasis
- Reserve Pin
- Stratix® IV GX HSSI 0 PPM core clock setting
- Termination Control Block
- I/O Maximum Toggle Rate
- Weak Pull-Up Resistor
I/O Timing Logic Options:
- Auto Turbo Bit
- D1 Delay (I/O buffer to input register)
- D2 Delay (I/O buffer to input register or internal cells)
- D3Delay (I/O buffer to Internal Cells)
- D4Delay (DQS Delay Chain)
- D5Delay (output register to I/O buffer)
- D5 OCTDelay (OCT to I/O buffer)
- D6Delay (output register to I/O buffer)
- D6 OCT Delay (OCT to I/O buffer)
- Delay from Output Register to Output Pin
- DQS Bus to Input Register Delay
- Enable Beneficial Skew Optimization
- Far capacitance
- Far differential resistance (in ohms)
- Far pull-down resistance (in ohms)
- Far pull-up resistance (in ohms)
- Far series resistance (in ohms)
- Far transmission line distributed capacitance (in farads/inch)
- Far transmission line distributed inductance (henrys/inch)
- Far transmission line length (in inches)
- Fast Input Register
- Fast OCT Register
- Fast Output Enable Register
- Fast Output Register
- Near capacitance
- Near differential resistance (in ohms)
- Near pull-down resistance (in ohms)
- Near pull-up resistance (in ohms)
- Near series resistance (in ohms)
- Near transmission line distributed capacitance (in farads/inch)
- Near transmission line distributed inductance (henrys/inch)
- Near transmission line length (in inches)
- Optimize IOC Register Placement for Timing
- Optimize Timing
- Output Buffer Delay
- Output Buffer Delay control
- PLL External Feedback Board Delay
- Slew Rate
- T4 Delay (output register to switch multiplexer)
- T8 Delay (DQS to input register)
- T8 Delay (NDQS to input register)
- T11 Delay (DQS post-amble delay)
- Termination voltage (in volts)
Synthesis logic options:
- Add Pass-Through Logic to Inferred RAMs
- Allow Any RAM Size For Recognition
- Allow Any ROM Size For Recognition
- Allow Any Shift Register Size For Recognition
- Allow Synchronous Control Signals
- Allows Asynchronous Clear Usage For Shift Register Replacement
- Auto Carry Chains
- Auto Clock Enable Replacement
- Auto DSP Block Replacement
- Auto Gated Clock Conversion
- Auto Logic Cell Insertion
- Auto Open-Drain Pins
- Auto Packed Registers
- Auto Parallel Expanders
- Auto RAM Block Balancing
- Auto RAM Replacement
- Auto RAM to Logic Cell Conversion
- Auto RAM to MLAB Conversion
- Auto Resource Sharing
- Auto ROM Replacement
- Auto Shift Register Replacement
- Block Design Naming
- Carry Chain Length
- Clock MUX Protection
- Disable Register Merging
- DSP Block Balancing
- Equivalent RAM and MLAB Paused Read Capabilities
- Equivalent RAM and MLAB Power Up
- Extract Verilog State Machines
- Extract VHDL State Machines
- Force Use of Synchronous Clear Signals
- HDL Initial Fan-Out Limit
- HDL Message Level
- Ignore CARRY Buffers
- Ignore CASCADE Buffers
- Ignore LCELL Buffers
- Ignore Maximum Fan-out Assignments
- Ignore SOFT Buffers
- Ignore translate_off and synthesis_off Directives
- Ignore Verilog initial constructs
- Implement as Clock Enable
- Implement as Output of Logic Cell
- Insert Additional Logic Cell
- Iteration limit for constant Verilog loops
- Iteration limit for non-constant Verilog loops
- Logic Cell Insertion
- Maximum DSP Block Usage
- Maximum Fan-Out
- Maximum Number of M4K/M9K Memory Blocks
- NOT Gate Push-Back
- Number of Removed Registers Reported in Synthesis Report
- Optimization Technique
- Perform WYSIWYG Primitive Resynthesis
- Power-Up Don't Care
- Power-Up Level
- PowerPlay® Power Optimization (Analysis & Synthesis Settings Page)
- Preserve Fan-out Free Register Node
- Preserve Registers
- Remove Duplicate Registers
- Remove Redundant Logic Cells
- Restructure Multiplexers
- Safe State Machine
- Show Parameter Settings Tables in Synthesis Report
- Speed Optimization Technique for Clock Domains
- State Machine Processing
- Timing Driven Synthesis
Simulation logic options:
Fitter optimization:
- Auto Delay Chains
- Auto Global Clock
- Auto Global Register Control Signals
- Auto Merge PLLs
- Auto RAM to MLAB Conversion
- Automatic Asynchronous Signal Pipelining -- Allow Asynchronous Signal that Fans Out to Synchronous Inputs
- Enable Bus-Hold Circuitry
- Equivalent RAM and MLAB Power Up
- Exclusive I/O Group
- External LVDS Receiver Uses DPA
- Final Placement Optimizations
- Fitter Aggressive Routability Optimizations
- Optimize Design for Metastability
- Optimize IOC Register Placement for Timing
- Perform automatic asynchronous signal pipelining
- Perform register duplication
- Perform register retiming
- Placement Effort Multiplier
- Programmable Power Maximum High-Speed Fraction of Used LAB Tiles
- Programmable Power Technology Optimization
- Router Timing Optimization Level
Other:
- Always Enable Input Buffers
- Auto Register Duplication
- Automatic Asynchronous Signal Pipelining -- Allow Asynchronous Signal that Fans Out to Synchronous Inputs
- Automatic Asynchronous Signal Pipelining Register Reach
- Data[0] Pin
- DCLK Pin
- Disable Message
- EDA Formal Verification Hierarchy
- Enable Design Assistant Rule
- Enable Message
- Force Merging of PLL Clock Fanouts
- Input Delay from Dual-Purpose Clock Pin to Fan-Out Destinations
- Input Delay from Pin to Input Register
- Input Delay from Pin to Internal Cells
- Input Reference
- Input Termination
- Output Enable Pin Delay
- Partition Hierarchy
- Power Analyzer Report Power Dissipation
- Power Analyzer Report Signal Activity
- Power Input File Settings
- PowerPlay® Power Optimization (Fitter Settings Page)
- SCE Pin
- SDO Pin
- Treat Bidirectional Pin as Output Pin
- Turbo Bit
- Use Checkered Pattern as Uninitialized RAM Content