Verilog HDL Synthesis Support

Quartus^® Prime synthesis supports the following Verilog HDL language standards:

• Verilog-1995 (IEEE Standard 1364-1995)
• Verilog-2001 (IEEE Standard 1364-2001)

The following important guidelines apply to Quartus^® Prime synthesis of Verilog HDL:

• The Compiler uses the Verilog-2001 standard by default for files with an extension of .v.
• If you use scripts to add design files, you can use the -HDL_VERSION command to specify the HDL version for each design file.
• Compiler support for Verilog HDL is case sensitive in accordance with the Verilog HDL standard.
• The Compiler supports the compiler directive `define, in accordance with the Verilog HDL standard.
• The Compiler supports the include compiler directive to include files with absolute paths (with either “/” or “\” as the separator), or relative paths.
• When searching for a relative path, the Compiler initially searches relative to the project directory. If the Compiler cannot find the file, the Compiler next searches relative to all user libraries. Finally, the Compiler searches relative to the current file's directory location.
• Quartus^® Prime Pro Edition synthesis searches for all modules or entities earlier in the synthesis process than other Quartus software tools. This earlier search produces earlier syntax errors for undefined entities than other Quartus software tools.

Quartus^® Prime support for Verilog HDL is described for the following categories of Verilog HDL constructs. These sections match those in the IEEE Std 1364-2001 IEEE Hardware Description Language Based on the Verilog Hardware Description Language manual.