Input Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
|
Yes |
Clock for the address register. |
The |
arclkena |
No |
Clock enable signal for the |
Intel recommends changing the clock enable signal at the rising edge of the |
|
Yes |
Input for the address register. |
The |
|
Yes |
Shift signal for the address register. |
The |
|
Yes |
Clock for the data register. |
The |
drclkena |
No |
Clock enable signal for the |
Intel recommends changing the clock enable signal at the rising edge of the |
|
Yes |
Input for the data register. |
The |
|
Yes |
Shift signal for the data register. |
The |
|
Yes |
Signal that controls the erase sequence. |
The |
|
No |
Signal that enables the internal oscillator. |
The |
|
No |
Signal that initiates a program sequence. |
The |