Input Ports

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Port Name	Required	Description	Comments
`aclr`	No	Asynchronous clear input.	If the `aclr` port is connected, the `aset` port cannot be used.
`aset`	No	Asynchronous set input	If the `aset` port is connected, the `aclr` port cannot be used.
`datain_h[]`	Yes	Input data to be output to the `padio` port at the rising edge of the `outclock` port.	Input port `[NUMBER_OF_DQ - 1..0]` wide.
`datain_l[]`	Yes	Input data to be output to the `padio` port at the falling edge of the `outclock` port.	Input port `[NUMBER_OF_DQ - 1..0]` wide.
`inclock`	Yes	Clock input that drives the data strobe.
`inclocken`	No	Clock enable for the `inclock` port
`oe`	No	Output enable signal.	The `oe` port defaults to `VCC` when enabled.
`outclock`	Yes	Clock signal for the output and oe registers.
`outclocken`	No	Clock enable signal for each clock port.