Verilog HDL Example Instantiation

module test (datain_h, datain_l, oe, outclock, dataout, dataout_n);

       input   datain_h;

       input   datain_l;

       input   outclock;

       input oe;

       output   dataout;

       output   dataout_n;

       wire tmp_out;

       wire tmp_oe;

 

       my_altddio_out altddio_out_inst (

                                                 .outclock (outclock),

                                                 .datain_h (datain_h),

                                                 .datain_l (datain_l),

                                                 .dataout (tmp_out),

                                                 .aclr (1'b0),

                                                 .aset (1'b0),

                                                 .oe (oe),

                                                 .outclocken (1'b1),

                                                 .oe_out (tmp_oe),

                                                 .sclr (1'b0)

                                           );

 

alt_outbuf_tri_diff my_outbuf (.i (tmp_out), .oe (tmp_oe), .o(dataout), .obar(dataout_n));

defparam my_outbuf.io_standard = "LVDS";

 

endmodule