Verilog HDL Example Instantiation

alt_outbuf    my_outbuf
          (.i(internal_sig), .o(out)); //out must be declared as an    output pin    defparam
        my_outbuf.io_standard = "2.5 V";    defparam
        my_outbuf.slow_slew_rate = "on";    defparam
        my_outbuf.enable_bus_hold = "on";    defparam
        my_outbuf.weak_pull_up_resistor = "off";    defparam
        my_outbuf.termination = "series 50 ohms";