preserve VHDL Synthesis Attribute
A VHDL synthesis attribute that prevents Analysis &
Synthesis from minimizing or removing a particular register. You
can use this synthesis attribute to preserve a register for later
observation with the
Quartus® Prime Simulator or the
Signal Tap Logic Analyzer. You can also use this synthesis
attribute to prevent register optimizations to a preliminary
version of your design. For example, if a register's input is a
constant VCC, Analysis & Synthesis may use the Power-Up
Don't Care logic option to minimize the register away
completely. By setting the preserve
synthesis attribute on the register, you can prevent this
optimization.
The preserve
synthesis attribute does not prevent register duplication or
register packing optimizations from occurring. Duplication and
register packing optimizations are reported in the Analysis
& Synthesis Netlist Optimizations report and the
Fitter Netlist
Optimizations report when they occur. To prevent all
optimizations to a register, see the help documentation on the
Netlist
Optimizations logic option.
syn_preserve
. This synthesis attribute behaves identically to the
preserve
synthesis attribute.
There are two important limitations of the preserve
synthesis attribute:
- It prevents a register from being inferred as a state machine.
- It does not preserve fanout-free registers. Use the
noprune
synthesis attribute to prevent Analysis & Synthesis from removing fanout-free registers.
You cannot use this synthesis attribute for registers that have no fan-out.
To use the preserve synthesis attribute, you must first declare
the attribute in the local scope or import its declaration from the
altera_syn_attributes
package in the altera
library. You can then use an attribute specification to associate
the attribute with a signal or variable that infers a register in
your design. For example, in the following code, the attribute
declaration declares the preserve attribute as a boolean object in
the local scope, and the attribute specification associates the
preserve
synthesis attribute with the signal reg1
:
signal reg1: stdlogic; attribute preserve: boolean; attribute preserve of reg1: signal is true;
You can also set the preserve
synthesis attribute on an entity or architecture, causing Analysis
& Synthesis to preserves all registers in the entity or
architecture, except registers that infer state machines.