multstyle VHDL Synthesis Attribute
A VHDL synthesis attribute that specifies the implementation
style for multiplication operations (*
) in your HDL
source. Using this attribute, you can control whether the
Quartus® Prime software should preferentially implement a
multiplication operation in general logic or dedicated hardware, if
available in the target device.
syn_multstyle
. This synthesis attribute behaves identically to the
multstyle
synthesis attribute.
To use the multstyle
attribute in a VHDL Design File (.vhd) Definition, you must first declare the attribute with
a string
type using an Attribute Declaration. Then
associate the synthesis attribute with a signal, variable, entity,
or architecture. The attribute value should be either
"logic"
or "dsp"
, indicating a preferred
implementation in logic or in dedicated hardware, respectively.
dsp
" for the
Quartus® Prime software to
implement as multiplication in dedicated hardware if one operand is a constant and
you
are not multiplying by a power of 2. The final implementation depends on the
availability of dedicated hardware in the target device.
When applied to an entity or architecture, the attribute
specifies the default implementation style for all instances of the
*
operator in the entity or architecture. For example,
in the following code, the multstyle
attribute directs
the
Quartus® Prime software to use dedicated hardware, if
possible, for all multiplications inside architecture
rtl
of entity foo
.
entity foo is
...
end foo;
architecture rtl of foo is
attribute multstyle : string;
attribute multstyle of rtl : architecture is "dsp";
begin
...
end rtl;
When applied to a signal or variable, the attribute specifies
the implementation style to be used for all instances of the
*
operator whose result is directly assigned to the
signal or variable. It overrides the multstyle
attribute associated with the enclosing entity or architecture, if
present. For example, in the following code, the
multstyle
attribute associated with signal
res
directs the
Quartus® Prime software to implement the
a * b
in general logic rather than dedicated
hardware.
signal a, b : unsigned(8 downto 0);
signal res : unsigned(17 downto 0);
attribute multstyle : string;
attribute multstyle of res : signal is "logic";
res <= a * b;