SRFFE Primitive
The SRFFE primitive allows you to specify an
SR-type flipflop with clock enable.
Note: When the
ENA (clock enable) input is high, the flipflop passes a
signal that is dependent on the S and R inputs to
Q. When the ENA input is low, the state of
Q is maintained, regardless of the S and
R inputs.
For devices that do not support clock enable, logic synthesis generates logic equations containing flipflops with clock enables. These logic equations correctly emulate the logic specified in the project.
Note: For information about
Quartus® Prime primitive instantiation, go to Using a
Quartus® Prime
Logic Function.