Performing a Timing Simulation with the VCS Software
To perform a timing simulation of a Quartus® Prime generated Verilog Output File (.vo) Definition and the corresponding Standard Delay Format Output File (.sdo) Definition with the Synopsys® VCS software:
The EDA Netlist Writer generates a functional simulation netlist rather than a timing simulation netlist for designs that specify the Stratix® V or newer device families, even if you specified a timing simulation netlist.
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If your design contains high-speed elements such as GXB blocks, you must use transport delay options to perform a timing simulation. You can add transport delay options for the VCS software when performing a timing simulation with Standard Delay Format Output File (.sdo) Definition. For more information on using transport delays, see the " Synopsys® VCS and VCS-MX Support" chapter in the Quartus® Prime Handbook, vol. 3.
- Intel recommends that you set Time scale settings to picoseconds (ps) in the interface or with command-line commands when performing timing simulations of designs with RAM.
- If your design contains the alt2gxb megafunction, refer to the alt2gxb Help topic for required settings information.