Generate Example Design (Generate Menu) (Qsys Pro)

You can generate a Qsys Pro example design by clicking Generate > Generate Example Design.

The example design provides the top-level HDL definition of your Qsys Pro system in either Verilog HDL or VHDL. This tab also displays VHDL component declarations. You can copy this HDL example and paste it into a top-level HDL file that instantiates the Qsys Pro system, if the system is not the top-level module in your Quartus^® Prime project.