To perform a timing simulation with command-line commands
To perform a timing simulation of a Verilog HDL or VHDL design with the Mentor Graphics QuestaSim software with command-line commands:
Note: You can use batch files to set up and compile each of the libraries automatically. Copy all the commands displayed in the QuestaSim main window into a text file and name the file with
a .do extension (that is, <file name>.do). Use this script to recompile the libraries if you update them.
To run a macro script:
- From the QuestaSim main window, chose Execute Macro.
- In the Execute Do File dialog box, locate your QuestaSim macro file (.do).
- Click Open.