To perform a timing simulation of a VHDL design with command-line commands
- If you have not already done so, perform Setting Up the Incisive Enterprise Simulator Working Environment.
-
To create a work library in the project directory, type the
following command at the command prompt:
mkdir <work library>
Note:Intel recommends using the IES (Verilog or VHDL) default library names when you create a library. You should name the IES software libraries as follows:
- When you run the IES software independently from the Quartus® Prime software, you should name your library work.
- When you run the IES software automatically from the Quartus® Prime software, your library is automatically named gate_work under the current project directory, and the work alias is mapped to the gate_work directory when performing gate level simulation.
- Copy the cds.lib and hdl.var files, which are located in the /<NCSim installation directory path>/tools/inca/files/ directory, to the /<project directory>/simulation/ncsim directory.
-
To map the <device
family> variable to a device-specific directory and to map the
work library to the physical location of the work library, add the following
lines to the cds.lib file:
DEFINE <device family> ./device family> DEFINE <work library> ./work
Note: Note: When you run the IES software automatically after compilation in the Quartus® Prime software, the IES software automatically performs steps 4 and 5. -
To annotate the timing data in the SDF Output File:
-
Compile the SDF Output File using the ncsdfc utility by typing the following
command at the command prompt:
ncsdfc <project name> _vhd.sdo
The ncsdfc utility generates a <project name>.sdf.X compiled SDF Output File and places it in the /<project directory>/simulation/ncsim directory.
-
Specify the compiled SDF Output File for the project by
adding the following line to the SDF command file for the project:
COMPILED_SDF_FILE = " <project name>.sdf.X
-
Specify the scope level by adding the following line to
the SDF command file:
SCOPE = : <instance name or lower-level entity being annotated for timing>
-
Compile the SDF Output File using the ncsdfc utility by typing the following
command at the command prompt:
-
To compile the appropriate project files and libraries into the
work library, type the following commands at the command prompt from within the
project directory:
To compile the .vho, testbench file (if you are using one), and the appropriate library model files, type the following commands at a command prompt:
ncvhdl -v93 -work <device family> /quartus/eda/sim_lib/<device family>_atoms.vhd ncvhdl -v93 -work <device family> /quartus/eda/sim_lib/<device family>_components.vhd ncvhdl <testbench file>.vhd ncvhdl <project name>.vho
-
To simulate high-speed circuits, including designs that use
HSSI, LVDS, and PLLs, type the following command at the command prompt to enable
transport delays:
ncelab -pulse_e 0 -pulse_r 0 -timescale "1ps/1ps" work.<top-level entity name>
Note: For more information about transport and inertial delays, refer to the NCSIM User Guide. -
To elaborate and simulate the design, type the following
commands at the command prompt:
ncelab -sdf_cmd_file <SDF command file name> <work library>.<top-level entity name> ncsim <work library>.<top-level entity name>
-
To direct the IES software to generate a .vcd that you can then use to perform power
analysis in the Quartus® Prime PowerPlay Power
Analyzer:
-
In the file explorer pane, select the
<testbench or design instance name>_dump_all_vcd_nodes.tcl
.tcl generated by the Quartus® Prime EDA Netlist Writer. - On the File menu, click Source. The .tcl directs the IES software to monitor and write the output signals contained in the .tcl to a .vcd during simulation.
-
In the file explorer pane, select the