Input Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
|
No |
Asynchronous clear for pipelined usage. |
The pipeline initializes to an undefined (X)
logic level. The |
|
No |
Clock for pipelined usage. |
The clock port provides pipelined operation
for the |
|
Yes |
Multiplicand. |
Input port |
|
No |
Clock enable for pipelined usage. |
If omitted, the default is 1. |