Input Ports
Port Name |
Required |
Description |
Comments |
---|---|---|---|
|
No |
Asynchronous set or reset signal for the DQS output and output enable registers. |
|
|
Yes |
Data input port for the DQS output register
which outputs on the rising edge of the |
Input port |
|
Yes |
Data input port for the DQS output register
which outputs on the falling edge of the |
Input port |
|
No |
Synchronous set or reset signal for the DQS output and output enable registers. |
|
|
Yes |
The system reference clock port that drives the DLL. |
|
|
No |
Output enable for the DQS output registers. |
The |
|
Yes |
Clock to the DQS output and output enable registers. |
|
|
No |
Clock enable port for the DQS output and oe registers. |
The |
|
No |
Data input for the DLL delay setting reset. |
Values are |