VHDL Component Declaration
The following VHDL component declaration is located in the VHDL Design File (.vhd) DefinitionALTERA_MF_COMPONENTS.vhdin the <Quartus® Prime installation directory>\libraries\vhdl\altera_mf directory.
component alt_oct
generic (
intended_device_family : string := "unused";
enable_parallel_termination : string := "FALSE";
oct_block_number : natural := 0;
power_down : string := "TRUE";
lpm_hint : string := "UNUSED";
lpm_type : string := "alt_oct"
);
port(
aclr : in std_logic := '0';
cal_shift_busy : out std_logic_vector(oct_block_number-1 downto 0);
calibration_busy : out std_logic_vector(oct_block_number-1 downto 0);
calibration_done : out std_logic_vector(oct_block_number-1 downto 0);
calibration_request : in std_logic_vector(oct_block_number-1 downto 0);
calibration_wait : in std_logic_vector(oct_block_number-1 downto 0) := (others => '0');
clken : in std_logic := '1';
clock : in std_logic;
parallelterminationcontrol : out std_logic_vector(oct_block_number * 14-1 downto 0);
rdn : in std_logic_vector(oct_block_number-1 downto 0);
rup : in std_logic_vector(oct_block_number-1 downto 0);
s2pload : in std_logic_vector(oct_block_number-1 downto 0);
seriesterminationcontrol : out std_logic_vector(oct_block_number * 14-1 downto 0);
termination_control : out std_logic_vector(16 * oct_block_number-1 downto 0)
);
end component;